module top( BTN_X,
			AN,
            B,
            G,
            HS,
            LED,
            R,
            SEGMENT,
            VS,
            beep,
            clk,
            ps2_clk,
            ps2_data,
            rst,
            BTN );

   /*******************************************************************************
   ** The inputs are defined here                                                **
   *******************************************************************************/
   input clk;
   input ps2_clk;
   input ps2_data;
   input rst;
   input BTN;

   /*******************************************************************************
   ** The outputs are defined here                                               **
   *******************************************************************************/
   output [3:0] AN;
   output [3:0] B;
   output [3:0] G;
   output       HS;
   output [7:0] LED;
   output [3:0] R;
   output [7:0] SEGMENT;
   output       VS;
   output       beep;
   output 		BTN_X;

   /*******************************************************************************
   ** The wires are defined here                                                 **
   *******************************************************************************/
   wire [1:0]  s_logisimBus0;
   wire [8:0]  s_logisimBus1;
   wire [3:0]  s_logisimBus10;
   wire [15:0] s_logisimBus12;
   wire [3:0]  s_logisimBus15;
   wire [3:0]  s_logisimBus16;
   wire [1:0]  s_logisimBus17;
   wire [3:0]  s_logisimBus19;
   wire [7:0]  s_logisimBus21;
   wire [3:0]  s_logisimBus25;
   wire [3:0]  s_logisimBus26;
   wire [3:0]  s_logisimBus29;
   wire [2:0]  s_logisimBus3;
   wire [11:0] s_logisimBus30;
   wire [11:0] s_logisimBus31;
   wire [9:0]  s_logisimBus4;
   wire [3:0]  s_logisimBus6;
   wire [7:0]  s_logisimBus9;
   wire        s_logisimNet11;
   wire        s_logisimNet13;
   wire        s_logisimNet14;
   wire        s_logisimNet18;
   wire        s_logisimNet2;
   wire        s_logisimNet20;
   wire        s_logisimNet22;
   wire        s_logisimNet27;
   wire        s_logisimNet28;
   wire        s_logisimNet5;
   wire        s_logisimNet7;
   wire        s_logisimNet8;

   /*******************************************************************************
   ** The module functionality is described here                                 **
   *******************************************************************************/

   /*******************************************************************************
   ** Here all wiring is defined                                                 **
   *******************************************************************************/
   assign s_logisimBus16[0]  = s_logisimBus31[0];
   assign s_logisimBus16[1]  = s_logisimBus31[1];
   assign s_logisimBus16[2]  = s_logisimBus31[2];
   assign s_logisimBus16[3]  = s_logisimBus31[3];
   assign s_logisimBus19[0]  = s_logisimBus31[8];
   assign s_logisimBus19[1]  = s_logisimBus31[9];
   assign s_logisimBus19[2]  = s_logisimBus31[10];
   assign s_logisimBus19[3]  = s_logisimBus31[11];
   assign s_logisimBus30[0]  = s_logisimBus19[0];
   assign s_logisimBus30[10] = s_logisimBus16[2];
   assign s_logisimBus30[11] = s_logisimBus16[3];
   assign s_logisimBus30[1]  = s_logisimBus19[1];
   assign s_logisimBus30[2]  = s_logisimBus19[2];
   assign s_logisimBus30[3]  = s_logisimBus19[3];
   assign s_logisimBus30[4]  = s_logisimBus6[0];
   assign s_logisimBus30[5]  = s_logisimBus6[1];
   assign s_logisimBus30[6]  = s_logisimBus6[2];
   assign s_logisimBus30[7]  = s_logisimBus6[3];
   assign s_logisimBus30[8]  = s_logisimBus16[0];
   assign s_logisimBus30[9]  = s_logisimBus16[1];
   assign s_logisimBus6[0]   = s_logisimBus31[4];
   assign s_logisimBus6[1]   = s_logisimBus31[5];
   assign s_logisimBus6[2]   = s_logisimBus31[6];
   assign s_logisimBus6[3]   = s_logisimBus31[7];
   assign BTN_X = 1'b0;
  
   /*******************************************************************************
   ** Here all input connections are defined                                     **
   *******************************************************************************/
   assign s_logisimNet13 = ps2_data;
   assign s_logisimNet14 = BTN;
   assign s_logisimNet28 = ps2_clk;
   assign s_logisimNet5  = clk;
   assign s_logisimNet7  = rst;

   /*******************************************************************************
   ** Here all output connections are defined                                    **
   *******************************************************************************/
   assign AN      = s_logisimBus29[3:0];
   assign B       = s_logisimBus25[3:0];
   assign G       = s_logisimBus10[3:0];
   assign HS      = s_logisimNet11;
   assign LED     = s_logisimBus21[7:0];
   assign R       = s_logisimBus26[3:0];
   assign SEGMENT = s_logisimBus9[7:0];
   assign VS      = s_logisimNet27;
   assign beep    = s_logisimNet22;

   /*******************************************************************************
   ** Here all in-lined components are defined                                   **
   *******************************************************************************/

   // 非门
   assign s_logisimNet8 = ~s_logisimNet7;

   // 非门
   assign s_logisimNet20 = ~s_logisimNet7;

   // 常量
   assign  s_logisimBus15[3:0]  =  4'hF;


   // 常量
   assign  s_logisimBus21[7:3]  =  {1'b1, 4'hF};


   /*******************************************************************************
   ** Here all sub-circuits are defined                                          **
   *******************************************************************************/

   clk_25M   clk_25M0 (.clk(s_logisimNet5),
                       .vga_clk(s_logisimNet18));

   VGA_ctrl   VGA_ctrl0 (.B(s_logisimBus25[3:0]),
                         .Din(s_logisimBus30[11:0]),
                         .G(s_logisimBus10[3:0]),
                         .HS(s_logisimNet11),
                         .R(s_logisimBus26[3:0]),
                         .VS(s_logisimNet27),
                         .clk(s_logisimNet18),
                         .col(s_logisimBus4[9:0]),
                         .rdn(),
                         .row(s_logisimBus1[8:0]),
                         .rst(s_logisimNet8));

   ps2_dlc   ps2_dlc0 (.clk(s_logisimNet5),
                       .dir(s_logisimBus17[1:0]),
                       .ps2_clk(s_logisimNet28),
                       .ps2_data(s_logisimNet13),
                       .rst(s_logisimNet7));

   gaming   gaming0 (.game_state(s_logisimBus0[1:0]),
                     .gameover(s_logisimNet2),
                     .rst(s_logisimNet7),
                     .start_button(s_logisimNet14));

   VGA_screen_pic   VGA_screen_pic0 (.clk(s_logisimNet5),
                                     .game_state(s_logisimBus0[1:0]),
                                     .pix_data_out(s_logisimBus31[11:0]),
                                     .pix_x(s_logisimBus4[9:0]),
                                     .pix_y(s_logisimBus1[8:0]),
                                     .state(s_logisimBus3[2:0]));

   run_module   run_module0 (.clk(s_logisimNet5),
                             .cur_x(s_logisimBus4[9:0]),
                             .cur_y(s_logisimBus1[8:0]),
                             .dir(s_logisimBus17[1:0]),
                             .fruit_state(s_logisimBus21[2:0]),
                             .game_state(s_logisimBus0[1:0]),
                             .gameover(s_logisimNet2),
                             .one_state(s_logisimBus3[2:0]),
                             .score(s_logisimBus12[15:0]));

   top_beep   top_beep0 (.beep(s_logisimNet22),
                         .clk(s_logisimNet5),
                         .game_state(s_logisimBus0[1:0]));

   DispNum   DispNum0 (.AN(s_logisimBus29[3:0]),
                       .LEs(s_logisimBus15[3:0]),
                       .SEGMENT(s_logisimBus9[7:0]),
                       .clk(s_logisimNet5),
                       .hexs(s_logisimBus12[15:0]),
                       .points(s_logisimBus15[3:0]),
                       .rst(s_logisimNet20));

endmodule